Parallel Architectures of the ASIC for Walsh-Hadamard Transform

The design of ASIC (Application-specified Integrated Circuit) has been recently paid a lot of attention to by scholars. In this paper,investigation was made in some respects related with the design of the ASIC for Walsh-Hadamard transform (WHT). These respects include the desing of the dedicated algorithma and their SFGs(Signal Flow Graphs),the design of the VLSI array, bit-string computation, and variable-size function. At the end, resonable VLSI array architecture was presented for the WHT ASIC.

Project Supported:

Clc Number:

TN911.7