Implementation of FIR Filter Using High Density Programmable Logic Device
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Abstract:
In order to accelerate the working speed of a FIR filter, the structure-optimized FIR filter, which includes a vector-multiplication that can efficiently reduce the numbers of multiplication and addition of tradition structure, has been deduced .The vector-multiplication can be realized easily by means of the LUT in HDPLD FLEX10K. Using development software of MAX+PLUS II, both parallel and serial parameteized FIR filter have been designed.
