Design of the Expandable (I)FFT Implemented in the CPLD
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Abstract:
The architecture of scalable length and high speed FFT processor based on CPLD(Complex Programmable Logic Device) is proposed, including the pipeline architecture of the radix mixed FFT algorithm, the address regularity of the read-then-write RAM, the array architecture of short-length FFT and the pipeline complement architecture of CORDIC(Coordinate Rotation Digital Computer) algorithm. If the input-data velocity is 20 MHz,the time expended on 1024-point FFT is 50 us.
