Highspeed, highprecision digital phasesensitive detector design for electrical impedance tomography
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Abstract:
Electrical impedance tomography (EIT) system must have the properties of high precision and speed, thus the digital phasesensitive detector (DPSD) based on the field programmable gate array(FPGA) is developed for data collection of EIT. Based on the principle of DPSD, the relationship between signaltonoise ratio (SNR) and sample resolution as well as total number of samples is deduced. An implementation scheme of this system and a method of designing analogtodigital converter (ADC) clock based on direct digital synthesis (DDS) technology are provided. The system adopts highspeed multichannel ADC and low jitter clock conditioner for ADC. Realtime DPSD is implemented with FPGA. The experiments show that the measurement accuracy reaches 0.03% and the SNR reaches 85 dB. The agar phantom experiments prove that the performance of the DPSD meet the designing requirement for EIT.
