LDPC encoding and decoding design based on Verilog HDL
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Abstract:
LDPC (low density parity check code) is one of the most excellent codes，and it is a strong competitor of the fourth generation communication system (4G) as its performance is close to Shannon transmission limit.The paper realizes LDPC encoding and decoding algorithm through Verilog to improve computational efficiency，and selects π rotation matrix construction method to encode.And queen algorithm avoids the appearance of Cyclotella in H matrix.The UMP BP-based algorithm is also used in decoding and all of decimal fractions are limited between -100 and 100.For a large number of decimal fractions，the Q8 (fixed-point) format is adopted to express them and the range is between -128 and 127.996 093 75 with the precision of 0.003 906 25.Thus floating-point arithmetic can be avoided and Verilog language can be used to describe the LDPC decoding algorithm.The program does not use any IP core，which means it can be applied to all FPGAs and has good transplantation.It has high application value in engineering.
