FPGA optimal implementation of AES based on Verilog HDL
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Abstract:
AES algorithm is a widely used cryptographic algorithm.To improve AES algorithm，it’s proposed to repeatedly call key expansion module to realize efficient use of the code.Ten-round keys are generated at the same time，and operations of add round key are achieved by the control module.The key is called repeatedly when the AES algorithm is running for encryption and decryption.The realization of AES is verified by modelsim6.1f.AES algorithm is designed with Verilog HDL，and a clear description about the critical core code realization of the process is proposed.The hardware implementation is verified by FPGA.Experimental results show that the optimized AES algorithm has only 3 531 slices，5 522 LUTs on a Xilinx Virtex-V FPGA.Our implementation occupies less area and it can get the same performance with comparing with other implementations of the AES，so it can meet application requirements of smaller chip，which can make the AES algorithm be applied to the popular small area on the smart card.It can make the AES algorithm use in the smart card.
