Design and process simulation of high voltage P-channel VDMOS
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Abstract:
As one of core devices in modern power semiconductor, P-channel VDMOS device has not been well researched for its narrow applications. We focused on the development of P-channel VDMOS device, designed a P-channel VDMOS with breakdown voltage over -200 V, including the active region cell structure and the junction termination structure, and developed a non-self-aligned progress flow for P channel VDMOS. Simulation results show that the breakdown voltage of the device is over -200 V and the threshold voltage is -2.78 V. The results meet the design requirements, and the research can provide references for the device fabrication.
