This paper designs a fast-locking and low-jitter clock and data recovery (CDR) circuit which can be applied to a 28Gb/s high-speed serial receiver. Via theories-based derivation, we built a mathematical model between loop parameters and loop stability, designed circuits and optimized the loop parameters on that basis. In order to solve the problem that the jitter performance and locking time of the clock cannot be achieved at the same time, a charge pump featuring automatic current switch is installed in a circuit structure where the proportional path is separated from the integral path. In this way, automatic adjustment of the loop bandwidth is accomplished, which equips the loop with low jitter and fast locking. Using Matlab simulation, we identified the factors that influenced the loop stability and validated our mathematical model. Through the Cadence Sepctre simulation, the locking takes about 450 ns and the value of the jitter peak is 2.3 ps. Compared with a CDR equipped with a traditional charge pump, the new CDR has shortened the locking time by 55% and reduced the jitter by 52%.