Investigation on failure mechanism and reliability improvement of fan-out panel level packaging under temperature cycling
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Affiliation:

1.University of Electronic Science and Technology of China;2.China Resources Microelectronics Limited;3.Chengdu University of Information Technology;4.Chongqing University

Clc Number:

TM23

Fund Project:

Postdoctoral Fellowship Program of CPSF

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    Abstract:

    Fan-out panel level packaging (FOPLP) has the advantages of high output rate, large exposure area, and low material loss, and is regarded as a representative of advanced packaging technology. However, due to the high-density integration of various materials and complex internal interconnection structures, the reliability of the FOPLP has been widely observed. In this paper, the reliability of FOPLP was investigated by combining multi-physics field simulation with temperature cycling tests, and a packaging optimization design was proposed. Firstly, a multi-level and multi-physics field coupling finite element simulation model was built based on the packaging structure. Secondly, the impact of component CTE was analyzed, and material matching schemes were investigated. Thirdly, the temperature cycling tests were performed, and the packaging failure mechanism was analyzed. Finally, the impact of packaging design parameters was investigated. A packaging optimization design was proposed and its reliability was validated through temperature cycling tests. The results indicated that the interface between the epoxy molding compound (EMC) on the chip surface and the heat sink was the weak point, where cracks were prone to occur and extended to the chip, ultimately leading to catastrophic failure. The stress in the low reliability components was effectively reduced by adding a 1.5 layer interconnect structure to increase the thickness of the EMC on the chip surface, thereby improving the reliability of FOPLP.

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History
  • Received:November 14,2024
  • Revised:December 20,2024
  • Adopted:February 13,2025
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