This paper proposes an optimized design method for a gate-isolated drive circuit of SiC MOSFETs based on planar coreless transformer technology. The circuit topology was first determined according to the requirements of high-voltage solid-state power controllers (SSPCs). Following this, key parameters such as trace width and coil diameter were defined under PCB fabrication constraints, and a near-field coupling model was established for co-simulation with peripheral circuits. Subsequently, circuit parameters were optimized through theoretical and simulation analysis, culminating in the fabrication and experimental evaluation of prototype samples. Experimental results demonstrated that the optimized design achieves a planar coreless transformer diameter reduction to 8 mm, transmission efficiency exceeding 83%, and SiC MOSFET switching times of ≤56 μs (turn-on) and ≤100 μs (turn-off). Additionally, the proposed circuit enables real-time switching state detection while exhibiting significantly enhanced noise immunity compared to conventional solutions, addressing critical challenges in miniaturization and high-performance power device control.