电阻抗成像对测量系统的精度和速度都有较高要求，为此研制了基于现场可编程门阵列(field programmable gate array, FPGA)的数字相敏检波器(digital phasesensitive detector , DPSD)用于电阻抗成像的数据测量。在分析DPSD原理的基础上，推导出信噪比与采样点数和采样分辨率的关系。给出了测量系统的实现方案，提出了基于直接数字频率合成(direct digital synthesis, DDS)技术的模数转换器(analogtodigital

Electrical impedance tomography (EIT) system must have the properties of high precision and speed, thus the digital phasesensitive detector (DPSD) based on the field programmable gate array(FPGA) is developed for data collection of EIT. Based on the principle of DPSD, the relationship between signaltonoise ratio (SNR) and sample resolution as well as total number of samples is deduced. An implementation scheme of this system and a method of designing analogtodigital converter (ADC) clock based on direct digital synthesis (DDS) technology are provided. The system adopts highspeed multichannel ADC and low jitter clock conditioner for ADC. Realtime DPSD is implemented with FPGA. The experiments show that the measurement accuracy reaches 0.03% and the SNR reaches 85 dB. The agar phantom experiments prove that the performance of the DPSD meet the designing requirement for EIT.

国家高技术研究发展计划(863计划)资助项目(2006AA02Z4B7);中俄国际合作项目(ISCP 2007DFR30080)