本文设计了一款应用于28Gb/s高速串口接收机的快速锁定、低抖动时钟数据恢复电路。通过理论推导,构建了环路参数与环路稳定性能的数学模型,并以该模型为指导,完成了电路设计和环路参数优化；为了解决时钟抖动性能和锁定时间难以兼顾的问题,在比例-积分通路分离的电路结构中,设计了一种能够自动切换电流的电荷泵,实现了环路带宽的自动调节,使得环路能够兼顾低抖动和快速锁定两种优势。通过MATLAB仿真,获得了稳定因子对于环路稳定性的影响,验证了所建立数学模型的正确性；通过Cadence Spectre仿真,获得了不同情况下环路的锁定时间以及时钟的抖动性能。当环路中使用自切换电流电荷泵时,锁定时间约为450ns,抖动峰峰值为2.3ps。相较于使用传统电荷泵的CDR,锁定时间缩短了55%,抖动降低了52%。

This paper designs a fast-locking and low-jitter clock and data recovery (CDR) circuit which can be applied to a 28Gb/s high-speed serial receiver. Via theories-based derivation, we built a mathematical model between loop parameters and loop stability, designed circuits and optimized the loop parameters on that basis. In order to solve the problem that the jitter performance and locking time of the clock cannot be achieved at the same time, a charge pump featuring automatic current switch is installed in a circuit structure where the proportional path is separated from the integral path. In this way, automatic adjustment of the loop bandwidth is accomplished, which equips the loop with low jitter and fast locking. Using Matlab simulation, we identified the factors that influenced the loop stability and validated our mathematical model. Through the Cadence Sepctre simulation, the locking takes about 450 ns and the value of the jitter peak is 2.3 ps. Compared with a CDR equipped with a traditional charge pump, the new CDR has shortened the locking time by 55% and reduced the jitter by 52%.

TN453