Silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) are favored by power electronics engineers for their excellent performance. However, the dynamic threshold voltage drift caused by the poor gate oxide quality of SiC MOSFETs poses a potential threat to their stable operation. Particularly under extreme conditions such as avalanche, the dynamic threshold voltage drift in parallel SiC MOSFETs significantly increases the likelihood of avalanche failure. To investigate the impact of dynamic threshold voltage drift on the avalanche behavior of parallel SiC MOSFETs, a dual parallel avalanche test platform was established. Using the method of separating variables, the avalanche current sharing of parallel SiC MOSFETs with different amounts of dynamic threshold voltage drift was studied. Experimental results indicate that when the threshold voltage difference between parallel SiC MOSFETs is small, the current sharing during avalanche is high. However, when the threshold voltage difference exceeds 0.5V, the current sharing during avalanche is poor, with the device having the smaller threshold voltage carrying more current during both the current rise and avalanche phases. It is believed that the device with the larger threshold voltage captures a significant amount of electrons, leading to a decrease in channel mobility and consequently lower avalanche current sharing.