1.电子科技大学;2.华润微电子有限公司;3.成都信息工程大学;4.重庆大学
TM23
国家资助博士后研究人员计划
1.University of Electronic Science and Technology of China;2.China Resources Microelectronics Limited;3.Chengdu University of Information Technology;4.Chongqing University
Postdoctoral Fellowship Program of CPSF
扇出型面板级封装具有高产出率、高曝光面积、低物料损耗等优势，是代表性先进封装技术，但受多种材料高密度集成、内部互联结构复杂等影响，其可靠性问题日益突出。针对扇出型面板级封装可靠性问题，结合多物理场仿真与温度循环实验，揭示封装失效机制，研究组件热膨胀系数、几何参数对可靠性影响，并提出加固设计方案。首先，基于扇出型面板级封装结构，建立多层级多物理场耦合有限元仿真模型；其次，分析组件热膨胀系数对封装可靠性影响，研究材料匹配方案；再次，开展温度循环实验，研究封装失效机制；最后，分析组件几何参数对封装可靠性影响，提出可靠性加固设计方案，并通过温度循环实验予以验证。研究结果表明，芯片表面塑封料与散热片交界处是封装可靠性薄弱部位，裂纹易于此处产生并延伸至芯片，最终导致封装失效。通过1.5层互联结构设计增厚芯片表面塑封料厚度，可有效降低可靠性薄弱部位应力，提升封装可靠性。
Fan-out panel level packaging (FOPLP) has the advantages of high output rate, large exposure area, and low material loss, and is regarded as a representative of advanced packaging technology. However, due to the high-density integration of various materials and complex internal interconnection structures, the reliability of the FOPLP has been widely observed. In this paper, the reliability of FOPLP was investigated by combining multi-physics field simulation with temperature cycling tests, and a packaging optimization design was proposed. Firstly, a multi-level and multi-physics field coupling finite element simulation model was built based on the packaging structure. Secondly, the impact of component CTE was analyzed, and material matching schemes were investigated. Thirdly, the temperature cycling tests were performed, and the packaging failure mechanism was analyzed. Finally, the impact of packaging design parameters was investigated. A packaging optimization design was proposed and its reliability was validated through temperature cycling tests. The results indicated that the interface between the epoxy molding compound (EMC) on the chip surface and the heat sink was the weak point, where cracks were prone to occur and extended to the chip, ultimately leading to catastrophic failure. The stress in the low reliability components was effectively reduced by adding a 1.5 layer interconnect structure to increase the thickness of the EMC on the chip surface, thereby improving the reliability of FOPLP.
