Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power modules are highly sensitive to packaging parasitic inductance in high-frequency and high-speed switching applications. Excessive parasitic inductance can cause voltage overshoot, current oscillation, increased switching losses, and intensified electromagnetic interference. To address this issue, this paper proposes an optimized power terminal structure based on reverse coupling, which effectively reduces packaging parasitic inductance while maintaining compatibility with standard module layouts. By redesigning the power terminal geometry, anti-parallel current paths are formed between adjacent conductors to enhance mutual inductance cancellation and suppress the total inductance. Simulation results show that the packaging parasitic inductance decreases from 21.86?nH to 10.67?nH after optimization, and the new structure also exhibits good performance in insulation withstand voltage and thermal stress. To verify the effectiveness of the proposed method, a prototype was fabricated and tested. Double-pulse testing yielded a value of 12.67?nH, and vector network analyzer (VNA) measurements indicated 11.61?nH, representing a 46.9% reduction compared with the standard structure. These results confirm the feasibility of the proposed method in engineering applications and provide a new approach for developing low-cost, low-inductance packaging for SiC power modules.