1.重庆理工大学，电子与电气工程学院;2.重庆平创半导体研究院有限责任公司
重庆市教委科学技术研究项目(KJQN202301123)。
1.School of Electrical and Electronic Engineering,Chongqing University of Technology;2.Chongqing Pingchuang Institute of Semiconductors Co,Ltd
Supported by the Science and Technology Research Program of Chongqing Municipal Education Commission (Grant No.KJQN202301123).
碳化硅（Silicon Carbide，SiC）金属氧化物半导体场效应晶体管（Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET）功率模块在高频高速开关应用中对封装寄生电感极为敏感，过大的寄生电感不仅会引发电压尖峰、电流振荡，还会增加开关损耗并加剧电磁干扰。为此，本文提出一种基于反向耦合的功率端子结构优化方法，在兼容现有标准封装形式的基础上，有效降低封装寄生电感。该方法通过重新设计功率端子结构，使相邻导体之间形成反向电流路径，从而增强互感抵消效应，降低总寄生电感。仿真结果表明，优化前封装寄生电感为21.86 nH，优化后降至10.67 nH，且新结构在绝缘耐压与热应力方面表现良好。为验证其有效性，本文制作了优化样品并开展实验测试，双脉冲测试结果为12.67 nH，矢量网络分析仪（Vector Network Analyzer, VNA）测试结果为11.61 nH，较标准结构降低约46.9%。该结果验证了所提方法在工程实践中的可行性，为实现低成本、低寄生电感的SiC功率模块封装提供了新思路。
Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power modules are highly sensitive to packaging parasitic inductance in high-frequency and high-speed switching applications. Excessive parasitic inductance can cause voltage overshoot, current oscillation, increased switching losses, and intensified electromagnetic interference. To address this issue, this paper proposes an optimized power terminal structure based on reverse coupling, which effectively reduces packaging parasitic inductance while maintaining compatibility with standard module layouts. By redesigning the power terminal geometry, anti-parallel current paths are formed between adjacent conductors to enhance mutual inductance cancellation and suppress the total inductance. Simulation results show that the packaging parasitic inductance decreases from 21.86?nH to 10.67?nH after optimization, and the new structure also exhibits good performance in insulation withstand voltage and thermal stress. To verify the effectiveness of the proposed method, a prototype was fabricated and tested. Double-pulse testing yielded a value of 12.67?nH, and vector network analyzer (VNA) measurements indicated 11.61?nH, representing a 46.9% reduction compared with the standard structure. These results confirm the feasibility of the proposed method in engineering applications and provide a new approach for developing low-cost, low-inductance packaging for SiC power modules.
