Because basic CMOS gates are widely employed in highperformance VLSI chips, we designed completely customized high performance 52bit orgates and 108bit andgates. HSPICE tools were used to simulate the circuits in a CSM 0.13 μm process, under 1.2 V power voltage at 25℃. Based on the features of different circuits, the corresponding input stimuli of the theoretically maximal delay were used for simulation. The frequency of the input stimulus was 1.25 GHz, while the skew was set as 10% of the input stimulus cycle. The input delay was the interval from 50% of input voltage to 50% of output voltage per cycle, and the maximal delay was the maximum of the delays of all input data. According to the different logic types, five types of 52bit orgates and two types of andgates were designed. Comparing with the simulation results, we conclude that the fully customized gates we designed are superior in many aspects such as speed, power, and area.