LDPC encoding and decoding design based on Verilog HDL
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摘要:
LDPC(low density parity check code)码是目前最优秀的码字之一，其接近香农传输极限的性能使其成为第四代通信系统(4G)强有力的竞争者。论文通过Verilog实现LDPC编译码算法从而提高运算效率，选用了“π旋转矩阵构造法”进行编码，“皇后算法”较好的避免了H矩阵中小环的出现。译码采用“UMP BP-Based(最小和或最大积)算法”，其中的对数运算将小数控制在了-100到100之间，对于运算过程中的大量小数均采用Q8(定点数)格式表示，范围-128≤X≤127.996 093 75，精度0.003 906 25，从而避免了浮点数运算，因此可以完全采用Verilog语言描述LDPC译码算法。程序中没有使用任何公司的IP核，适用于所有FPGA，可移植性好。
Abstract:
LDPC (low density parity check code) is one of the most excellent codes，and it is a strong competitor of the fourth generation communication system (4G) as its performance is close to Shannon transmission limit.The paper realizes LDPC encoding and decoding algorithm through Verilog to improve computational efficiency，and selects π rotation matrix construction method to encode.And queen algorithm avoids the appearance of Cyclotella in H matrix.The UMP BP-based algorithm is also used in decoding and all of decimal fractions are limited between -100 and 100.For a large number of decimal fractions，the Q8 (fixed-point) format is adopted to express them and the range is between -128 and 127.996 093 75 with the precision of 0.003 906 25.Thus floating-point arithmetic can be avoided and Verilog language can be used to describe the LDPC decoding algorithm.The program does not use any IP core，which means it can be applied to all FPGAs and has good transplantation.It has high application value in engineering.